1. Field of the Invention
The present invention relates to a semiconductor chip assembly, and more particularly to a method of connecting a conductive trace and an insulative base to a semiconductor chip.
2. Description of the Related Art
Semiconductor chips have input/output pads that must be connected to external circuitry in order to function as part of an electronic system. The connection media is typically an array of metallic leads (e.g., a lead frame) or a support circuit (e.g., a substrate), although the connection can be made directly to a circuit panel (e.g., a mother board). Several connection techniques are widely used. These include wire bonding, tape automated bonding (TAB) and.flip-chip bonding.
Wire bonding is by far the most common and economical connection technique. In this approach, wires are bonded, one at a time, from the chip to external circuitry by thermocompression, thermosonic or ultrasonic processes. In thermocompression bonding, fine gold wire is fed from a spool through a clamp and a capillary. A thermal source is swept past an end of the wire to form a wire ball that protrudes from the capillary. The chip or capillary is then heated to about 200 to 300xc2x0 C., the capillary is brought down over an aluminum pad, the capillary exerts pressure on the wire ball, and the wire ball forms a ball bond on the pad. The capillary is then raised and moved to a terminal on the support circuit, the capillary is brought down again, and the combination of force and temperature forms a wedge bond between the wire and the terminal. Thus, the connection between the pad and the terminal includes the ball bond (which only contacts the pad), the wedge bond (which only contacts the terminal) and the wire between the bonds. After raising the capillary again, the wire is ripped from the wedge bond, the thermal source is swept past the wire to form a new wire ball, and the process is repeated for other pads on the chip. Thermosonic bonding is similar to thermocompression bonding but adds ultrasonic vibration as the ball and wedge bonds are formed so that less heat is necessary. Ultrasonic bonding uses aluminum wire to form wedge bonds without applying heat. There are many variations on these basic methods.
TAB involves bonding gold-bumped pads on the chip to external circuitry on a polymer tape using thermocompression bonding. TAB requires mechanical force such as pressure or a burst of ultrasonic vibration and elevated temperature to accomplish metallurgical welding between the wires or bumps and the designated surface.
Flip-chip bonding involves providing pre-formed solder bumps on the pads, flipping the chip so that the pads face down and are aligned with and contact matching bond sites, and melting the solder bumps to wet the pads and the bond sites. After the solder reflows it is cooled down and solidified to form solder joints between the pads and the bond sites. Organic conductive adhesive bumps with conductive fillers in polymer binders have been used in place of solder bumps, but they do not normally form a metallurgical interface in the classical sense. A major advantage of flip-chip bonding over wiring bonding and TAB is that it provides shorter connection paths between the chip and the external circuitry, and therefore has better electrical characteristics such as less inductive noise, cross-talk, propagation delay and waveform distortion. In addition, flip-chip bonding requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space are used.
While flip-chip technology has tremendous advantages over wire bonding and TAB, its cost and technical limitations are significant. For instance, the cost of forming bumps on the pads is significant. In addition, an adhesive is normally underfilled between the chip and the support circuit to reduce stress on the solder joints due to thermal mismatch between the chip and the support circuit, and the underfilling process increases both manufacturing complexity and cost. Furthermore, the solder joints exhibit increased electrical resistance as well as cracks and voids over time due to fatigue from thermo-mechanical stresses.
Other techniques besides wire bonding, TAB and flip-chip bonding have been developed to connect chips to external circuitry without using wires, leads or bumps. Such techniques include thin film rerouting at the wafer, panel or module level, and attaching a pre-patterned substrate to the chip such that through-holes in the substrate expose the pads and selectively applying conductive material into the through-holes.
A typical thin film routing approach includes depositing a dielectric material on the chip, providing through-holes in the dielectric material that expose the pads, providing metallization in the through-holes that contacts the pads, and providing a top layer of conductive circuitry on the dielectric material that contacts the metallization. In this manner, the additional circuitry is fabricated on the chip. Drawbacks to this approach include complicated manufacturing requirements, high cost, and chip loss if the additional circuitry is defective. In particular, since the chip or wafer provides a substrate for the additional circuitry, chips will be lost if the additional circuitry falls to achieve certain quality and yield criteria. Unpredictable chip loss has prevented the wide spread adoption of this xe2x80x9cchip firstxe2x80x9d approach in volume production. Furthermore, if the process is not performed on wafers, the commercially available silicon wafer processing equipment may not be compatible with common tooling and handling techniques.
The semiconductor chip assembly is subsequently connected to another circuit such as a printed circuit board (PCB) or mother board during next level assembly. Different semiconductor assemblies are connected to the next level assembly in different ways. For instance, ball grid array (BGA) packages contain an array of solder balls, and land grid array (LGA) packages contain an array of metal pads that receive corresponding solder traces on the PCB.
Thermo-mechanical wear or creep of the solder joints that connect the semiconductor chip assembly to the next level assembly is a major cause of failure in most board assemblies. This is because non-uniform thermal expansion and/or contraction of different materials causes mechanical stress on the solder joints.
Thermal mismatch induced solder joint stress can be reduced by using materials having a similar coefficient of thermal expansion (CTE). However, due to large transient temperature differences between the chip and other materials during power-up of the system, the induced solder joint stress makes the assembly unreliable even when the chip and the other materials have closely matched thermal expansion coefficients.
Thermal mismatch induced solder joint stress can also be reduced by proper design of the support circuit. For instance, BGA and LGA packages have been designed with pillar post type contact terminals that extend above the package and act as a stand-off or spacer between the package and the PCB in order to absorb thermal stress and reduce solder joint fatigue. The higher the aspect ratio of the pillar, the more easily the pillar can flex to follow expansion of the two ends and reduce shear stress.
Conventional approaches to forming the pillar either on a wafer or a separate support circuit include a bonded interconnect process (BIP) and plating using photoresist.
BIP forms a gold ball on a pad of the chip and a gold pin extending upwardly from the gold ball using a thermocompression wire bonder. Thereafter, the gold pin is brought in contact with a molten solder bump on a support circuit, and the solder is reflowed and cooled to form a solder joint around the gold pin. A drawback to this approach is that when the wire bonder forms the gold ball on the pad it applies substantial pressure to the pad which might destroy active circuitry beneath the pad. In addition, gold from the pin can dissolve into the solder to form a gold-tin intermetallic compound which mechanically weakens the pin and therefore reduces reliability.
U.S. Pat. No. 5,722,162 discloses fabricating a pillar by electroplating the pillar on a selected portion of an underlying metal exposed by an opening in photoresist and then stripping the photoresist. Although it is convenient to use photoresist to define the location of the pillar, electroplating the pillar in an opening in the photoresist has certain drawbacks. First, the photoresist is selectively exposed to light that initiates a reaction In regions of the photoresist that correspond to the desired pattern. Since photoresist is not fully transparent and tends to absorb the light, the thicker the photoresist, the poorer the penetration efficiency of the light. As a result, the lower portion of the photoresist might not receive adequate light to initiate or complete the intended photo-reaction. Consequently, the bottom portion of the opening in the photoresist might be too narrow, causing a pillar formed in the narrowed opening to have a diameter that decreases with decreasing height. Such a pillar has a high risk of fracturing at its lower portion in response to thermally induced stress. Furthermore, photoresist residue on the underlying metal might cause the pillar to have poor quality or even prevent the pillar from being formed. Second, if the photoresist is relatively thick (such as 100 microns or more), the photoresist may need to be applied with multiple coatings and receive multiple light exposures and bakes, which increases cost and reduces yield. Third, if the photoresist is relatively thick, the electroplated pillar may be non-uniform due to poor current density distribution in the relatively deep opening. As a result, the pillar may have a jagged or pointed top surface instead of a flat top surface that is better suited for providing a contact terminal for the next level assembly.
In view of the various development stages and limitations in currently available semiconductor chip assemblies, there is a need for a semiconductor chip assembly that is cost-effective, reliable, manufacturable, and provides excellent mechanical and electrical performance.
An object of the present invention is to provide a semiconductor chip assembly with a chip, a conductive trace and an insulative base that provides a low cost, high performance, high reliability package.
Another object of the present invention is to provide a convenient, cost-effective method for manufacturing semiconductor chip assemblies as column grid arrays or other structures.
In accordance with an aspect of the invention, a method of making a semiconductor chip assembly includes providing a semiconductor chip and a laminated structure, wherein the chip includes a conductive pad, the laminated structure includes a conductive trace, an insulative base and a metal base, the conductive trace includes a routing line and a pillar, the metal base and the routing line are disposed on opposite sides of the insulative base, and the pillar contacts the routing line and extends through the insulative base and into the metal base, removing a portion of the metal base that contacts the pillar, and forming a connection joint that contacts and electrically connects the conductive trace and the pad.
The method may include mechanically attaching the chip to the conductive trace using an insulative adhesive, and then forming a through-hole through the insulative base and the adhesive that exposes the routing line and the pad.
The method may also include positioning the conductive trace and the chip such that the routing line extends within and outside a periphery of the chip and the pillar is disposed outside the periphery of the chip.
The method may also include providing a metal layer in contact with the insulative base on a side opposite the metal base, forming a photoresist layer on the metal layer that selectively exposes a portion of the metal layer, etching the metal layer using the photoresist layer as an etch mask such that an unetched portion of the metal layer forms the routing line; and then removing the photoresist layer.
The method may also include forming a via that extends through the insulative base and into the metal base and the metal layer, depositing an electrically conductive material such as solder paste or conductive adhesive into the via, and then forming the pillar from the electrically conductive material, for instance by reflowing the solder paste or curing the conductive adhesive.
The method may also include mechanically drilling a hole through the the metal base, the insulative base and the metal layer to provide the via.
The method may also include providing a plug that seals the via at one end, depositing the electrically conductive material into the via from the unsealed end, forming the pillar from the electrically conductive material, and then removing the plug.
An advantage of the present invention is that the semiconductor chip assembly includes a conductive trace with an additively formed pillar that can be manufactured conveniently and cost effectively. Another advantage is that the insulative base can be provided before the metal base is etched, thereby enhancing the mechanical support and protection for the conductive trace when the metal base is etched. Another advantage is that the assembly can be manufactured using low temperature processes which reduces stress and improves reliability. A further advantage is that the assembly can be manufactured using well-controlled wet chemical processes which can be easily implemented by circuit board, lead frame and tape manufacturers. Still another advantage is that the assembly can be manufactured using materials that are compatible with copper chip requirements.
These and other objects, features and advantages of the invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follows.